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this is information on a product in full production. june 2014 docid15232 rev 7 1/30 VIPER16 fixed frequency viper? plus family datasheet - production data figure 1. typical application features ? 800 v avalanche rugged power section ? pwm operation with frequency jittering for low emi ? operating frequency: ? 60 khz for l type ? 115 khz for h type ? no need of auxiliary winding for low power application ? standby power < 30 mw at 230 v ac ? limiting current with adjustable set point ? on-board soft-start ? safe auto-restart after a fault condition ? hysteretic thermal shutdown application ? replacement of capacitive power supply ? auxiliary power supply for appliances, ? power metering ? led drivers description the device is an off-line converter with an 800 v avalanche ruggedness power section, a pwm controller, user defined overcurrent limit, protection against feedback network disconnection, hysteretic thermal protection, soft start up and safe auto restart after any fault condition. it is able to power itself directly from the rectified mains, eliminating the need for an auxiliary bias winding. advance frequency jittering reduces emi filter cost. burst mode operation and the devices very low consumption both help to meet the standard set by energy saving regulations. ',3 62 qduurz table 1. device summary order codes package packaging VIPER16ln dip-7 tube VIPER16hn VIPER16hd so16 narrow tube VIPER16hdtr tape and reel VIPER16ld tube VIPER16ldtr tape and reel www.st.com
contents VIPER16 2/30 docid15232 rev 7 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 high voltage current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11 adjustable current limit set point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 12 fb pin and comp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13 burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14 automatic auto restart after overload or short-circuit . . . . . . . . . . . . . 20 15 open loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid15232 rev 7 3/30 VIPER16 contents 30 16 layout guidelines and design recommendations . . . . . . . . . . . . . . . . 23 17 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
block diagram VIPER16 4/30 docid15232 rev 7 1 block diagram 2 typical power figure 2. block diagram table 2. typical power part number 230 v ac 85-265 v ac adapter (1) 1. typical continuous power in non vent ilated enclosed adapter measured at 50 c ambient. open frame (2) 2. maximum practical continuous power in an open frame design at 50 c ambient, with adequate heat sinking. adapter (1) open frame (2) VIPER16 9 w 10 w 5 w 6 w
docid15232 rev 7 5/30 VIPER16 pin settings 30 3 pin settings figure 3. connection diagram (top view) note: the copper area for heat dissipation has to be designed under the drain pins. $0y 1& 1$ '5$,1 '5$,1 '5$,1 '5$,1 '5$,1 '5$,1 table 3. pin description pin n. name function dip-7 so16 11-2gnd connected to the source of the internal power mosfet and controller ground reference. -4n.a. not available for user. this pin is mechanically connected to the controller die pad of the frame. in order to improve the noise immunity, is highly recommended connect it to gnd (pin 1-2). 2 5 vdd supply voltage of the control section. this pin provides the charging current of the external capacitor. 36lim this pin allows setting the drain current limitation to a lower value respect to i dlim , which is the default one. the limit can be reduced by connecting an external resistor between this pin and gnd. in case of high electrical noise, a capacitor could be connected between this pin and gnd, the capacitor value must be lower than 470 nf in order to not impact the functionality of the pin. the pin can be left open if default drain current limitation, i dlim , is used. 47fb inverting input of the internal trans conductance error amplifier. connecting the converter output to this pin through a single resistor results in an output voltage equal to the error amplifier reference voltage (see v fb_ref on table 8 ). an external resistors divider is required for higher output voltages.
pin settings VIPER16 6/30 docid15232 rev 7 58comp output of the internal trans conductance error amplifier. the compensation network have to be placed between this pin and gnd to achieve stability and good dynamic performance of the voltage control loop. the pin is used also to directly control the pwm with an optocoupler. the linear voltage range extends from v compl to v comph ( table 8 ). 7,8 13-16 drain high voltage drain pin. the built-in high voltage switched start-up bias current is drawn from this pin too. pins connected to the metal frame to facilitate heat dissipation. table 3. pin description (continued) pin n. name function dip-7 so16
docid15232 rev 7 7/30 VIPER16 electrical data 30 4 electrical data 4.1 maximum ratings 4.2 thermal data table 4. absolute maximum ratings symbol pin (dip-7) parameter value unit min max v drain 7, 8 drain-to-source (ground) voltage 800 v e av 7, 8 repetitive avalanche energy (limited by t j = 150 c) 2 mj i ar 7, 8 repetitive avalanche current (limited by t j = 150 c) 1 a i drain 7, 8 pulse drain current (limited by t j = 150 c) 2.5 a v comp 5 input pin voltage -0.3 3.5 v v fb 4 input pin voltage -0.3 4.8 v v lim 3 input pin voltage -0.3 2.4 v v dd 2 supply voltage -0.3 self limited v i dd 2 input current 20 ma p tot power dissipation at t a < 40 c (dip-7) 1 w power dissipation at t a < 60 c (so16n) 1 w t j operating junction temperature range -40 150 c t stg storage temperature -55 150 c esd (hbm) 1 to 8 human body model 4 kv esd (cdm) 1 to 8 charge device model 1.5 kv table 5. thermal data symbol parameter max value so16n max value dip-7 unit r thjp thermal resistance junction pin (dissipated power = 1 w) 35 40 c/w r thja thermal resistance junction ambient (dissipated power = 1 w) 90 110 c/w r thja thermal resistance junction ambient (1) (dissipated power = 1 w) 1. when mounted on a standard single side fr4 board with 100 mm 2 (0.155 sq in) of cu (35 m thick) 80 90 c/w
electrical data VIPER16 8/30 docid15232 rev 7 4.3 electrical characteristics (t j = -25 to 125 c, v dd = 14 v (a) ; unless otherwise specified) a. adjust v dd above v ddon start-up threshold before setting to 14 v table 6. power section symbol parameter test condition min typ max unit v bvdss break-down voltage i drain = 1 ma, v comp = gnd, t j = 25 c 800 v r ds(on) drain-source on state resistance i drain = 0.2 a, t j = 25 c 20 24 i drain = 0.2 a, t j = 125 c 40 48 c oss effective (energy related) output capacitance v drain = 0 to 640 v 10 pf i off off state drain current v drain = 640 v v fb = gnd 60 a v drain = 800 v v fb = gnd 75 a table 7. supply section symbol parameter test condition min typ max unit voltage v drain _start drain-source start voltage 40 50 60 v i ddch1 start up charging current v drain = 100 v to 640 v, v dd = 4 v -0.6 -1.8 ma i ddch2 charging current during operation v drain = 100 v to 640 v, v dd = 9 v falling edge -7 -14 ma v dd operating voltage range 11.5 23.5 v v ddclamp v dd clamp voltage i dd = 15 ma 23.5 v v ddon v dd start up threshold 12 13 14 v v ddcson vdd on internal high voltage current generator threshold 9.5 10.5 11.5 v v ddoff v dd under voltage shutdown threshold 7 8 9 v
docid15232 rev 7 9/30 VIPER16 electrical data 30 current i dd0 operating supply current, not switching f osc = 0 khz, v comp = gnd 0.6 ma i dd1 operating supply current, switching v drain = 120 v, f sw = 60 khz 1.3 ma v drain = 120 v, f sw = 115 khz 1.5 ma i ddoff operating supply current with v dd < v ddoff v dd < v ddoff 0.35 ma i ddol open loop failure current threshold v dd = v ddclamp v comp = 3.3 v, 4 ma table 7. supply section (continued) symbol parameter test condition min typ max unit table 8. controller section symbol parameter test condition min typ max unit error amplifier v ref_fb fb reference voltage 3.2 3.3 3.4 v i fb_pull up current pull up -1 a g m trans conductance 2 ma/v current setting (lim) pin v lim_low low level clamp voltage i lim = -100 a0.5v compensation (comp) pin v comph upper saturation limit t j = 25 c 3 v v compl burst mode threshold t j = 25 c 1 1.1 1.2 v v compl_hys burst mode hysteresis t j = 25 c 40 mv h comp v comp / i drain 4 9 v/a r comp(dyn) dynamic resistance v fb = gnd 15 k i comp source / sink current v fb > 100 mv 150 a max source current v comp = gnd, v fb = gnd 220 a current limitation i dlim drain current limitation i lim = -10 a, v comp = 3.3 v, t j = 25 c 0.38 0.4 0.42 a t ss soft-start time 8.5 ms t on_min minimum turn on time 220 450 ns i dlim_bm burst mode current limitation v comp = v compl 85 ma overload t ovl overload time 50 ms t restart restart time after fault 1 s
electrical data VIPER16 10/30 docid15232 rev 7 oscillator section f osc switching frequency VIPER16l 54 60 66 khz VIPER16h 103 115 127 khz f d modulation depth f osc = 60 khz 4 khz f osc = 115 khz 8 khz f m modulation frequency 230 hz d max maximum duty cycle 70 80 % thermal shutdown t sd thermal shutdown temperature (1) 150 160 c t hyst thermal shutdown hysteresis (1) 30 c 1. specification assured by design, characterization and statistical correlation. table 8. controller section (continued) symbol parameter test condition min typ max unit
docid15232 rev 7 11/30 VIPER16 typical electrical characteristics 30 5 typical electrical characteristics figure 4. idlim vs t j figure 5. f osc vs t j figure 6. v drain_start vs t j figure 7. h comp vs t j figure 8. g m vs t j figure 9. v ref_fb vs t j ,'olp ,'olp# ?& 7->?&@ $0y $0y )26&)26&#?& 7->?&@ $0y 9 '5$ , 1 b 67 $ 5 7 9 '5 $ ,1 b 67 $5 7 # ?& 7->?&@ $0y 7->?&@ $0y *0 *0 # ?& 7->?&@ $0y 95()b)%95()b)%#?& 7->?&@
typical electrical characteristics VIPER16 12/30 docid15232 rev 7 figure 10. i comp vs t j figure 11. operating supply current (no switching) vs t j figure 12. operating suppl y current (switching) vs t j figure 13. idlim vs r lim figure 14. power mosfet on-resistance vs t j figure 15. power mosfet break down voltage vs t j $0y ,&20 3 ,&20 3#?& 7->?&@ $0y ,'','' #?& 7->?&@ $0y ,'' ,''#?& 7->?&@ $0y ,' o lp , ' ol p# .2kp 5olp >n2kp @
docid15232 rev 7 13/30 VIPER16 typical electrical characteristics 30 figure 16. thermal shutdown t j v dd i drain v ddon time v ddcson v ddoff t sd time time t sd - t hyst shut down after over temperature normal operation normal operation
typical circuit VIPER16 14/30 docid15232 rev 7 6 typical circuit figure 17. buck converter figure 18. buck boost converter $0y &21752/ )% '5$,1 *1' 9'' &203 /,0 0 9,3hu & / $&,1 & 'rxw &rxw /rxw &ie ' 5ie & 5ie &frps 5frps 5/,0 & rswlrqdo 5lq 'lq ' rswlrqdo 9287 *5281' &/,0 rswlrqdo $0y &21752/ )% '5$,1 *1' 9'' &203 /,0 0 9,3hu &/,0 rswlrqdo 'lq & 5lq $&,1 / & /rxw 'rxw &rxw & 5ie 5ie ' & 5frps &frps 9287 *5281' 5/,0 rswlrqdo ' rswlrqdo
docid15232 rev 7 15/30 VIPER16 typical circuit 30 figure 19. flyback converter (primary regulation) figure 20. flyback converter (non isolated) $0y &21752/ )% '5$,1 *1' 9'' &203 /,0 0 9,3hu &/,0 rswlrqdo & ' &fo 5dx[ 9287 &9'' 5/,0 &f $&,1 'dx[ )86( ' 5f & $&,1 &s 5ieo / 5iek &rxw &ie 5fo rswlrqdo ' $0y 'rxw 5/,0 *5281' rswlrqdo rswlrqdo *5281' ' 5g &g &rxw & $&,1 5lq / & &frps 5frps &frps 5ie 5ie & 9287 'dx[ 'lq %5,'*( &21752/ )% '5$,1 *1' 9'' &203 /,0 0 9,3hu &/,0 rswlrqdo
power section VIPER16 16/30 docid15232 rev 7 7 power section the power section is implemented with an n-channel power mosfet with a breakdown voltage of 800 v min. and a typical r ds(on) of 20 . it includes a sensefet structure to allow a virtually lossless current sensing and the thermal sensor. the gate driver of the power mosfet is designed to supply a controlled gate current during both turn-on and turn-off in order to minimize common mode emi. during uvlo conditions, an internal pull-down circuit holds the gate low in order to ensure that the power mosfet cannot be turned on accidentally. 8 high voltage current generator the high voltage current generator is supplied by the drain pin. at the first start up of the converter it is enabled when the voltage across the input bulk capacitor reaches the v drain_start threshold, sourcing a i ddch1 current (see table 7 on page 8 ); as the v dd voltage reaches the v ddon threshold, the power section starts switching and the high voltage current generator is turned off. the VIPER16 is powered by the energy stored in the v dd capacitor. in steady state condition, if the self biasing function is used, the high voltage current generator is activated between v ddcson and v ddon (see table 7 on page 8 ), delivering i ddch2 , see table 7 on page 8 to the v dd capacitor during the mosfet off time (see figure 21 on page 16 ). the device can also be supplied through the auxiliary winding; in this case the high voltage current source is disabled during steady-state operation, provided that vdd is above v ddcson . at converter power-down, the v dd voltage drops and the converter activity stops as it falls below v ddoff threshold (see table 7 on page 8 ). figure 21. power on and power off i dd v dd v drain v ddon t t t t v in v drain_start t t power-on power-off normal operation regulation is lost here v in < v drain_start hv startup is no more activated with internal self-supply without internal self-supply v ddcson v ddoff i ddch1 i ddch2
docid15232 rev 7 17/30 VIPER16 oscillator 30 9 oscillator the switching frequency is internally fixed at 60 khz (part number VIPER16ln or ld) or 115 khz (part number VIPER16hn or hd). in both cases the switching frequency is modulated by approximately 4 khz (60 khz version) or 8 khz (115 khz version) at 230 hz (typical) rate, so that the resulting spread- spectrum action distributes the energy of each harmonic of the switching frequency over a number of sideband harmonics having the same energy on the whole but smaller amplitudes. 10 soft start-up during the converters' start-up phase, the soft-start function progressively increases the cycle-by-cycle drain current limit, up to the default value i dlim . by this way the drain current is further limited and the output voltage is progressively increased reducing the stress on the secondary diode. the soft-start time is internally fixed to t ss , see typical value on table 8 on page 9 , and the function is activated for any attempt of converter start-up and after a fault event. this function helps prevent transformers' saturation during start-up and short-circuit. 11 adjustable current limit set point the VIPER16 includes a current mode pwm controller: cycle by cycle the drain current is sensed through the integrated resistor r sense and the voltage is applied to the non inverting input of the pwm comparator, see figure 2 on page 4 . as soon as the sensed voltage is equal to the voltage derived from the comp pin, the power mosfet is switched off. in parallel with the pwm operations, the comparator ocp, see figure 2 on page 4 , checks the level of the drain current and switch off the power mosfet in case the current is higher than the threshold i dlim , see table 8 on page 9 . the level of the drain current limit, i dlim , can be reduced depending from the sunk current from the pin lim. the resistor r lim , between lim and gnd pins, fixes the current sunk and than the level of the current limit, i dlim , see figure 13 on page 12 . when the lim pin is left open or if the r lim has an high value (i.e. > 80 k ) the current limit is fixed to its default value, i dlim , as reported on table 8 on page 9 .
fb pin and comp pin VIPER16 18/30 docid15232 rev 7 12 fb pin and comp pin the device can be used both in non-isolated and in isolated topology. in case of non- isolated topology, the feedback signal from the output voltage is applied directly to the fb pin as inverting input of the internal error amplifier having the reference voltage, v ref_fb, see the table 8 on page 9 . the output of the error amplifier sources and sinks the current, i comp , respectively to and from the compensation network connected on the comp pin. this signal is then compared, in the pwm comparator, with the signal coming from the sensefet; the power mosfet is switched off when the two values are the same on cycle by cycle basis. see the figure 2 on page 4 and the figure 22 on page 18 . when the power supply output voltage is equal to the error amplifier reference voltage, v ref_fb , a single resistor has to be connected from the output to the fb pin. for higher output voltages the external resistor divider is needed. if the voltage on fb pin is accidentally left floating, an internal pull-up protects the controller. the output of the error amplifier is externally accessible through the comp pin and it?s used for the loop compensation: usually an rc network. as reported on figure 22 on page 18 , in case of isolated power supply, the internal error amplifier has to be disabled (fb pin shorted to gnd). in this case an internal resistor is connected between an internal reference voltage and the comp pin, see the figure 22 on page 18 . the current loop has to be closed on the comp pin through the opto-transistor in parallel with the compensation network. the v comp dynamics ranges is between v compl and v comph as reported on figure 23 on page 19 . when the voltage v comp drops below the voltage threshold v compl , the converter enters burst mode, see section 13 on page 19 . when the voltage v comp rises above the v comph threshold, the peak drain current will reach its limit, as well as the deliverable output power. figure 22. feedback circuit fb comp without isolation: switch open & e/a enabled with isolation: switch closed & e/a disabled no isolation v out + - pwm stop from r sense r isolation r l nr sw v ref r comp + - e/a bus + - to pwm v compl r h v ref_fb
docid15232 rev 7 19/30 VIPER16 burst mode 30 13 burst mode when the voltage v comp drops below the threshold, v compl , the power mosfet is kept in off state and the consumption is reduced to i dd0 current, as reported on ta ble 7 o n page 8 . as reaction at the energy delivery stop, the v comp voltage increases and as soon as it exceeds the threshold v compl + v compl_hys , the converter starts switching again with consumption level equal to i dd1 current. this on-off operation mode, referred to as ?burst mode? and reported on figure 24 on page 19 , reduces the average frequency, which can go down even to a few hundreds hertz, thus minimizing all frequency-related losses and making it easier to comply with energy saving regulations. during the burst mode, the drain current limit is reduced to the value i dlim_bm (reported on table 8 on page 9 ) in order to avoid the audible noise issue. figure 24. load-dependent operating modes: timing diagrams figure 23. comp pin voltage versus i drain $0y 9 &203 , '5$,1 , , 'olpbep 'olp 9 &203+ 9 &203/ time time time v comp v compl +v compl_hys v compl i dd1 i dd0 i dd i drain i dlim_bm burst mode am13269v1
automatic auto restart after overload or short-circuit VIPER16 20/30 docid15232 rev 7 14 automatic auto restart after overload or short-circuit the overload protection is implemented in automatic way using the integrated up-down counter. every cycle, it is incremented or decremented depending if the current logic detects the limit condition or not. the limit condition is the peak drain current, i dlim , reported on table 8 on page 9 or the one set by the user through the r lim resistor, as reported in figure 13 on page 12 . after the reset of the counter, if the peak drain current is continuously equal to the level i dlim , the counter will be incremented till the fixed time, t ovl , after that will be disabled the power mosfet switch on. it will be activated again, through the soft start, after the t restart time, see the figure 25 and figure 26 on page 20 and the mentioned time values on table 8 on page 9 . in case of overload or short-circuit event, the power mosfet switching will be stopped after a time that depends from the counter and that can be as maximum equal to t ovl . the protection will occur in the same way until the overload condition is removed, see figure 25 and figure 26 on page 20 . this protection ensures restart attempts of the converter with low repetition rate, so that it works safely with extremely low power throughput and avoiding the ic overheating in case of repeated overload events. if the overload is removed before the protection tripping, the counter will be decremented cycle by cycle down to zero and the ic will not be stopped. figure 25. timing diagram: olp sequence (ic externally biased) figure 26. timing diagram: olp sequence (ic internally biased) am13270v1 time time v dd v ddon v ddcson i drain i dlim_bm t 1 * * the time t 1 can be lower or equal to the time t ovl t restart t ss t ovl t restart t ss t ovl t restart t ss short circuit occurs here short circuit removed here am13271v1 time time v dd v ddon v ddcson i drain i dlim_bm t 1 * * the time t 1 can be lower than or equal to the time t ovl t restart t ss t ovl t restart t ss t ovl t restart t ss short circuit occurs here short circuit removed here
docid15232 rev 7 21/30 VIPER16 open loop failure protection 30 15 open loop failure protection in case the power supply is built in fly-back topology and the VIPER16 is supplied by an auxiliary winding, as shown in figure 27 on page 21 and figure 28 on page 22 , the converter is protected against feedback loop failure or accidental disconnections of the winding. the following description is applicable for the schematics of figure 27 on page 21 and figure 28 on page 22 , respectively the non-isolated fly-back and the isolated fly-back. if r h is opened or r l is shorted, the VIPER16 works at its drain current limitation. the output voltage, v out , will increase and so the auxiliary voltage, v aux , which is coupled with the output through the secondary-to-auxiliary turns ratio. as the auxiliary voltage increases up to the internal v dd active clamp, v ddclamp (the value is reported on table 8 on page 9 ) and the clamp current injected on vdd pin exceeds the latch threshold, i ddol (the value is reported on table 8 on page 9 ), a fault signal is internally generated. in order to distinguish an actual malfunction from a bad auxiliary winding design, both the above conditions (drain current equal to the drain current limitation and current higher than i ddol through vdd clamp) have to be verified to reveal the fault. if r l is opened or r h is shorted, the output voltage, v out , will be clamped to the reference voltage v ref_fb (in case of non isolated fly-back) or to the external tl voltage reference (in case of isolated fly-back). figure 27. fb pin connection for non-isolated fly-back v compl d aux nr fb vdd v aux comp + - to pwm r l + - e/a r h r r aux c vdd v out r s v ref_fb from r sense bus + - pwm stop c s c p am13272v1
open loop failure protection VIPER16 22/30 docid15232 rev 7 figure 28. fb pin connection for isolated fly-back am13273v1 v ref_fb r h c comp + - pwm stop r 3 r tl r aux r comp c vdd - comp + - e/a nr r l v ref c c u5 disabled v aux v out + - to pwm sw fb r opto bus d aux v compl from r sense r c
docid15232 rev 7 23/30 VIPER16 layout guidelines and design recommendations 30 16 layout guidelines and design recommendations a proper printed circuit board layout is essential for correct operation of any switch-mode converter and this is true for the VIPER16 as well. also some trick can be used to make the design rugged versus external influences. careful component placing, correct traces routing, appropriate traces widths and compliance with isolation distances are the major issues. the main reasons to have a proper pcb routing are: ? provide a noise free path for the signal ground and for the internal references, ensuring good immunity against external noises and switching noises ? minimize the pulsed loops (both primary and secondary) to reduce the electromagnetic interferences, both radiated and conducted and passing more easily the emc regulations. the below list can be used as guideline when designing a smps using VIPER16. ? signal ground routing should be routed separately from power ground and, in general, from any pulsed high current loop; ? connect all the signal ground traces to the power ground, using a single "star point", placed close to the ic gnd pin; ? with flyback topologies, when the auxiliary winding is used, it is suggested to connect the vdd capacitor on the auxiliary return and then to the main gnd using a single track; ? the compensation network should be connected as close as possible to the comp pin, maintaining the trace for the gnd as short as possible; ? a small bypass capacitor (a few hundreds pf up to 0.1 f) to gnd might be useful to get a clean bias voltage for the signal part of the ic and protect the ic itself during eft/esd tests. a low esl ceramic capacitor should be used, placed as close as possible to the vdd pin; ? when using so16 package it is recommended to connect the pin 4 to gnd pin, using a signal track, in order to improve the noise immunity. this is highly recommended in case of high nosily environment; ? an optional capacitor can be connected on the lim pin in order to improve the ic noise immunity. it is strongly recommended to don't exceed 470nf. ? the ic thermal dissipation takes place through the drain pins. an adequate heat sink copper area has to be designed under the drain pins to improve the thermal dissipation; ? it is not recommended to place large copper areas on the gnd pins. ? minimize the area of the pulsed loops (primary, rcd and secondary loops), in order to reduce its parasitic self- inductance and the radiated electromagnetic field: this will greatly reduce the electromagnetic interferences produced by the power supply during the switching.
layout guidelines and design recommendations VIPER16 24/30 docid15232 rev 7 figure 29. suggested routing for converter: flyback case figure 30. suggested routing for converter: buck case 237,21$/ $& $& 9287 *1' )% &203 '5$,1 *1' &21752/ 9'' /,0 1$ 9,3(5 )% &203 '5$,1 *1' &21752/ 9'' /,0 1$ 9,3(5 237,21$/ $& $& 9287 *1'
docid15232 rev 7 25/30 VIPER16 package mechanical data 30 17 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 31. dip-7 package dimensions
package mechanical data VIPER16 26/30 docid15232 rev 7 1- the leads size is comprehensive of the thickness of the leads finishing material. 2- dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side). 3- package outline exclusive of metal burrs dimensions. 4- datum plane ?h? coincident with the bottom of lead, where lead exits body. 5- ref. poa mother doc. 0037880 6- creepage distance > 800 v 7- creepage distance 250 v 8- creepage distance as shown in the 664-1 cei / iec standard. table 9. dip-7 mechanical data dim. mm typ min max a 5,33 a1 0,38 a2 3,30 2,92 4,95 b 0,46 0,36 0,56 b2 1,52 1,14 1,78 c 0,25 0,20 0,36 d 9,27 9,02 10,16 e 7,87 7,62 8,26 e1 6,35 6,10 7,11 e 2,54 ea 7,62 eb 10,92 l 3,30 2,92 3,81 m (6)(8) 2,508 n 0,50 0,40 0,60 n1 0,60 o (7)(8) 0,548
docid15232 rev 7 27/30 VIPER16 package mechanical data 30 figure 32. so16n package dimensions
package mechanical data VIPER16 28/30 docid15232 rev 7 table 10. so16n mechanical data dim. mm min typ max a 1.75 a1 0.1 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 9.8 9.9 10 e 5.866.2 e1 3.8 3.9 4 e 1.27 h 0.25 0.5 l 0.4 1.27 k 0 8 ccc 0.1
docid15232 rev 7 29/30 VIPER16 revision history 30 18 revision history s table 11. document revision history date revision changes 21-jan-2009 1 initial release 07-dec-2009 2 updated figure 7 on page 11 14-may-2010 3 updated figure 3 on page 5 and table 3 on page 5 26-aug-2010 4 updated table 3 on page 5 , figure 16 on page 13 and figure 21 on page 16 10-oct-2011 5 updated figure 32 on page 27 and table 7 on page 8 26-may-2014 6 updated the features in cover page, table 3: pin description , table 4: absolute maximum ratings , table 6: power section , table 7: supply section . modified figure 17 , 18 , 19 and 20 . added section 16: layout guidelines and design recommendations . minor text changes. 13-jun-2014 7 updated table 3: pin description and table 6: power section . minor text changes.
VIPER16 30/30 docid15232 rev 7 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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